#ifndef __MACH_IMX9_REGS_H
#define __MACH_IMX9_REGS_H

#define MX9_I2C3_BASE_ADDR		0x42530000UL
#define MX9_I2C4_BASE_ADDR		0x42540000UL
#define MX9_UART3_BASE_ADDR		0x42570000UL
#define MX9_UART4_BASE_ADDR		0x42580000UL
#define MX9_UART5_BASE_ADDR		0x42590000UL
#define MX9_UART6_BASE_ADDR		0x425a0000UL
#define MX9_UART7_BASE_ADDR		0x42690000UL
#define MX9_UART8_BASE_ADDR		0x426a0000UL
#define MX9_I2C5_BASE_ADDR		0x426b0000UL
#define MX9_I2C6_BASE_ADDR		0x426c0000UL
#define MX9_I2C7_BASE_ADDR		0x426d0000UL
#define MX9_I2C8_BASE_ADDR		0x426e0000UL
#define MX9_SYSCNT_CTRL_BASE_ADDR	0x44290000UL
#define MX9_I2C1_BASE_ADDR		0x44340000UL
#define MX9_I2C2_BASE_ADDR		0x44350000UL
#define MX9_UART1_BASE_ADDR		0x44380000UL
#define MX9_UART2_BASE_ADDR		0x44390000UL
#define MX9_IOMUXC_BASE_ADDR		0x443c0000UL
#define MX9_CCM_BASE_ADDR		0x44450000UL
#define MX9_SRC_BASE_ADDR		0x44460000UL
#define MX9_ANATOP_BASE_ADDR		0x44480000UL
#define MX9_ANATOP_DRAM_PLL_BASE_ADDR	0x44481300UL
#define MX9_OCOTP_BASE_ADDR		0x47510000UL
#define MX9_S3MUA_BASE_ADDR		0x47520000UL
#define MX9_TRDC_NICMIX_BASE_ADDR	0x49010000UL
#define MX9_DDRMIX_BLK_CTRL_BASE	0x4E010000UL
#define MX9_DDR_PHY_BASE		0x4E100000UL
#define MX9_DDR_CTL_BASE		0x4E300000UL
#define MX9_DDR_CSD1_BASE_ADDR		0x80000000UL

#endif /* __MACH_IMX9_REGS_H */
